WLP Key Technology: RDL
WLP Key Technology: Bumping
Bumping Processes
Bumping generally refers to all bump preparation processes. The main preparation methods mainly include electroplating, printing, and ball mounting. Main technical indicators: bump pitch, bump diameter, bump height, conventional FC bumping achieves mass production with a minimum pitch of 80um, and micro bumping 40um mass production was achieved, and 25um pitch was completed.
WLP Key Technology : TSV
Through Silicon Via(TSV)
The TSV process is currently mainly used in silicon interposer, WLP packaging of MEMS/CIS/fingerprint chips, and 3D packaging of digital chips such as memory chips. The main technical indicators of the TSV process are aspect ratio, minimum hole spacing, etc. At present, the TSV process has achieved a 10:1 aspect ratio straight hole, and the deep hole TSV can be mass-produced, and the metal in the hole is filled with no holes. The remaining 3:1 straight hole TSV and other via last processes can also be mass-produced and passed the reliability test.
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Circuit-Chip provides advanced semiconductor substrates, packaging and engineering support for high-performance electronic applications. Our capabilities cover IC substrate design and fabrication, advanced packaging, simulation, testing, reliability support and selected high-density interconnect solutions for applications such as optical communication, AI computing, RF and industrial electronics.
